In optical fiber transmission systems the trend is to increase the data rate further to exploit the high transmission capacity of single-mode optic fibers. The limiting factor for data rate increases is usually not the data carrying capacity of the optical fiber, but rather electronic circuit performance. In digital communication networks, such as fiber optic transmission systems, the bit sampling clock signal is usually recovered from the incoming serial bit stream. A clock recovery anal bit sampling circuit well suited to interface with this invention is described in U.S. patent application Ser. No. 853,215, filed on Mar. 16, 1992now issued on Apr. 25, 1994 as U.S. Pat. No. 5,301,196, the teaching of which is incorporated herein by reference. At the communication link receiving end, the transmitted serial bit stream must be regenerated and deserialized. In many such communication systems, a phase locked loop (PLL) is used for recovery of the clock signal that corresponds in frequency and phase to the rate of the bit stream transmitted through the network and received at the station. Data deserialization is typically accomplished by a special circuit called the deserializer. The PLL and deserializer are considered to be critical components in the data communication network. These circuits traditionally operate at the serial bit stream rate and usually limit communication channel data carrying capability.
The present invention, therefore, is designed to solve this performance limitation of conventional digital data regeneration and deserialization techniques, and thus allows higher bit rate signal processing for a given system.
In the near future there will be a need for densely packaged arrays of high speed serial link electronics. It will be desirable to merge these functions with the slower link adaptor functions on a single chip. To reach that goal there is a need for a deserializer with the following attributes:
1. Maximum operating rate for a given technology and maximum given rate and technology. PA0 2. No or minimal reliance on delay tracking. PA0 3. Minimum power dissipation. PA0 4. Flawless operational characteristics (no `glitches` of any kind). PA0 5. Compatibility with LSSD testing strategies. PA0 6. Support of on-line intermittent fault isolation techniques.
The use of parity for diagnostic purposes has been implemented before:
W. F.. Tutt, "Parity Generate and Check Circuit", Technical Disclosure Bulletin, 25, No. 5, 2695-2697, IBM, October (1982). PA1 F. D. Ferraiolo and L. H. Wilson, "Error Detection/Fault Isolation for a Fiber-Optic Communication lank Using Parity", Technical Disclosure Bulletin, 33, No. 12, 38-39, IBM. May (1991). PA1 R. M. Chambers, "Deserializer For Serial Data Links", RESEARCH DISCLOSURE, No. 255, 25535, Kenneth Mason Publications Ltd., England, July (1985). PO883-0453 WSR P200 40-500. PA1 Hans-Martin Rein, "Multi-Gigabit-Per-Second Bipolar IC's for Future Optical-Fiber Transmission Systems", Journal of Solid State Circuits, 23, No. 3, 664-675. IEEE, June (1988). PA1 F. R. Gfeller, "Gbit/s serialiser/deserialiser subsystem For GaAs large-scale optoelectronic integration", Proceedings, 136, Pt.G., No. 4, 721-227, IEEE, August (1989). PA1 R. L. Deremer, L. W. Freitag, D. W. Siljenberg, and J. T. Trnka, "High Speed Word Recognizer for a Serial Shift Register", Technical Disclosure Bulletin, 33, No. 5, 407-410, IBM, October (1990). PA1 Dennis T. Kong, "2.488 Gb/s SONET Multiplexer/Demultiplexer with Frame Detection Capability", Journal on Selected Areas in Communications, 9, No. 5, 726-731, IEEE, June (1991). PA1 R. B. Nubling, James Yu, Keh-Chung Wang, Peter M. Asbeck, Neng-Haung Sheng, Mau-Chung F. Chang, R. I. Pierson, G. J. Sullivan, Mark A. McDonald, A. J. Price, and A.D.M. Chen, "High-Speed 8:1 Multiplexer and 1:8 Demultiplexer Implemented with AlGaAs/GaAs HBT's", Journal of Selected Areas in Communications, 26, No. 10, 1354-1361, IEEE, October (1991).
However, the circuits proposed previously would seriously limit the maximum operating rate and could not be modified readily for use in a deserializer structure as described herein.
Known deserializers which generally do not meet one or more of the above requirements are described in:
Before transmission on a line, data is encoded to simplify the transmitter and receiver circuits and to improve the reliability of the data transfer. For this purpose an 8 bit byte is often translated into a constrained sequence of 10 bits.
When data is transmitted from the sending location to the receiving location, the receiving location must synchronize the clocks of the receiving system to the transmitted data so that it can be properly read. The first level of synchronization is at the bit level, usually implemented by a PLL. This level of synchronization is a prerequisite for the present invention and not a subject of it. The next level of required synchronization is at the byte level. The receiver must find the boundaries of successive coded bytes in the serial bit stream and present one or more bytes in a parallel format aligned with the byte boundaries at the output. The current invention addresses systems with constrained coded bit streams that contain a unique bit sequence for the unambiguous identification of the byte boundaries. The unique bit sequence is usually referred to as the comma. The data may be further structured as 4-byte words and as frames containing a variable number of words. The start and end of a frame are commonly marked by a special word with a comma in the first byte position. An important function of the deserializer is to find the comma in the bit stream and to align the parallel output of the deserializer so that the first bit of a byte and the first byte of a worst appear always on the same output lines.
FIG. 1 schematically shows a conventional deserializer for 10-bit bytes such as described in the articles of Deremer et al., and Gfeller, cited above. To identify the byte boundary in a serial bit stream 10, serial data stream 10 is fed into memory locations 0, 1, 2, 3, 4, 5, 6, 7, 8 and 9 which can be part of a conventional shift register. These ten memory locations contain 10 bits D0, D1, D2, D3, D4, D5, D6, D7, D8 and D9. Circuitry represented by lines 12 connect the memory cells 0-9 to circuit 14 which monitors the ten memory locations 0-9 to determine when the comma character appears. At that time D0 is in cell 0, D1 in cell 1, . . . , and D9 in cell 9 for just one bit period. The bits D0-D9 are shifted through the memory locations 0-9 as represented by arrows 16 in a manner similar to that of a shift register. The bits in the input stream 10 pass through the bit cells 0-9 at the rate of the input stream 10, therefore, the circuitry 12 and 14 must be as fast as the bit rate to be able to read the bits stored in memory locations 0-9. As the transmission rate of communication lines increases, the cost of manufacturing circuitry to read the bits to locate the comma at the bit rate goes up significantly since high speed circuits are generally very costly. In the byte boundary locating system of FIG. 1, when the comma is found, the system clock is set to correspond to the byte boundary, to indicate the time when 10 bits belonging to a single byte are present in the memory locations 0-9 for parallel readout. The byte clock is then said to be synchronized with the input byte stream. This technique is characterized by a constant read-out location of data from the serial register and by variable timing, i.e. the clock is adjusted to catch the data at the right time.
FIG. 2 shows another commonly used technique (which is described in the article of Gfeller cited above) For locating the byte boundary of input stream 20. It is characterized by a constant byte clock, but variable read-out location. i.e. the the read-out location is varied to fit the timing of the clock. In FIG. 2, 20 memory locations, such as 0, 1, 2, . . . , 18, and 19 hold two sets of bits D0-D9. In this configuration a first circuit 40 is connected by lines 45 to the first 10 bit locations corresponding to cells 0-9. Another circuit 44 is connected by lines 46 to a second set of 10 bit locations 1-10. A third, fourth. etc. circuit can be connected to a third or fourth set of ten memory locations, each set incremented by one cell location number. The input sequential bit stream 20 is fed into the memory locations 0-19, and the circuits 40 and 44, and lines 42 and 46 simultaneously monitor the first set of ten bit locations and the second set of bit locations, respectively. When the comma is detected by circuit 40 or 42, or when any subsequent similar circuits corresponding to other sets of ten bit locations identify the comma, the system fixes which one of the circuits such as 40 or 44 is to read out the set of 10 bits. The system clock is not changed. The circuits 44 in combination with lines 46, and circuit 40 in combination with lines 42 must operate at the bit rate of input stream 20, since the bits are passed through memory locations 0-19, as represented by arrows 70, at the same rate as the input stream 20. Therefore, the circuits and lines 40, 42, 44 and 46 must have a speed equal to that of the input data rate in order to properly identify the comma. Here again, as the transmission speed of the bits increases, the circuits necessary to identify the comma using the scheme of FIG. 2 substantially increase the cost. There is also a very large number of circuits required for this solution. The circuits require a heavy drive from the register and the clock drivers, which limits its operating speed.